risc-v isa simulator

March, 2020 - May, 2020


Worked on this project in a team of 4 during my college course of Computer Architecture and got a bagged of 100%.

Developed a Simulator Program in C++ to convert the Assembly Language input to a Machine Code, executed using Memory and Register Arrays for storing data and variables.

To improve the performance by enabling parallel execution of instructions, the simulator supports various functionalities including Data Forwarding, Flushing, Pipelining and Branch Prediction.

Minimized stalling while preventing Data Hazards with the help of Data and Memory Buffers.

Github Link


Pipelining - Buffer Prefetch

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